Semiconductor technology is constantly improving. Pioneer manufacturers have started mass production of 22/20nm process products, and are still developing 15nm technology aimed at mass production in 2 ~ 3 years. However, although technology is constantly improving, many technicians have a sense of isolation. Because the key to technological innovation-miniaturization is worrying. The etching technology that determines the success or failure of micronization has not found a breakthrough, and the cost advantage brought by micronization is more and more difficult to confirm. On the other hand, in 2011, there was a topic of great concern. Intel announced the practical application of three-dimensional transistors, and TSMC announced the construction of a 450mm wafer production line. These technologies are gradually expanding to the whole industry.
It is too late to adopt EUV lithography technology in mass production.
"Mass production of 22nm process products began in 2011. In 2013 and 2015, 14nm and 10nm process products will be mass-produced, respectively, and "process development will maintain the speed of advancing one generation in two years". The pioneers showed no signs of slowing down the pace of refinement, that is, "continuing Moore's Law". But there is still a sense of isolation in the industry. The reason is that the cost effect that should have been obtained through miniaturization is becoming more and more difficult to feel.
The reason why the semiconductor industry has been promoting miniaturization for decades is that miniaturization is like a "universal magic weapon". That is to say, all aspects such as performance, power consumption and cost can be improved at the same time only by miniaturization. However, this universal magic weapon gradually receded with the advancement of miniaturization. First of all, it is difficult to reduce power consumption only by miniaturization. Secondly, it is difficult to improve the performance only by miniaturization. At present, the performance is improved by introducing various boost technologies (technologies aimed at improving transistor performance) while realizing miniaturization. But the cost advantage is about to reach its limit.
The main reason why it is more and more difficult to achieve cost advantage is the rising cost of etching. In the future miniaturization, EUV lithography, which is expected by the industry, has not been put into practical use as a technology that can restrain the increase of etching cost and realize miniaturization. Therefore, high-cost etching technology has to be used to mass-produce semiconductors. In 22/20nm process products, companies adopt ArF immersion exposure technology instead of EUV lithography technology. Although EUV lithography is the first candidate for the 15nm process products that will be mass-produced in 2013 ~ 2014, ArF liquid immersion+secondary graphics (DP) technology has been prepared as a backup technology. However, these technical processes to extend the exposure life of ArF immersion are numerous and costly. If possible, I still hope to steadily promote the development of EUV lithography technology and use EUV lithography technology.
The output power of EUV light source cannot be improved.
The biggest reason why the development of EUV lithography can't make progress is that the output power of EUV light source is insufficient. If the output power of EUV light source is originally scheduled, it should be 100kW@IF (output at the middle focus position) in 2010 and 250kW@IF in 2012. However, as of the autumn of 2010, the research level data (Champion Data) is only about 20 ~ 40kW @ IF, which is far from the original goal. Therefore, companies engaged in the development of EUV light sources plan to turn the tide in 2011 and achieve their goals in 2011.
After entering 2011, this plan suffered setbacks from the beginning. In 2011, EUV exposure devices began to be equipped with light sources, which required practical output power rather than research-level data. As a result, the output power of 20 ~ 40 kW @ IF light source has not been improved, but has fallen into a dilemma of stagnation or even reduction. After that, through the efforts from spring to autumn, although the performance has been gradually improved, the final output power is only about 30kW@IF in practical level. Although the data has improved from research level to practical level, the absolute value of output power has hardly improved during the year.
There are two views among semiconductor technicians about such a slow speed. Some technicians think that EUV light source manufacturers are "children crying wolf", while others think that semiconductor manufacturers and exposure device manufacturers have put forward unrealistic schedule plans to EUV light source manufacturers. In any case, the implementation time of 100kW@IF has been delayed for another year until the middle of 2012. This means that the realization time of 250kW@IF required in the mass production stage will be later.
Judging from the current development situation of EUV light source, even if the future development is carried out according to the "Best Case" mentioned by EUV light source manufacturers, it is not certain whether it can barely catch up with the 15nm products that began mass production in 2013 ~ 2014. If the realization time will be delayed in the future, 15nm is needless to say, and it is unknown whether it can be used in the following 12 ~ 10 nm. Some people in the industry began to think that "the practical time of EUV lithography will be after 2018".
The delay of practical time brings a new topic for the practical application of EUV lithography. That is, there is a problem that the pattern size that can be resolved by EUV lithography deviates from the pattern size required for practical use. The light source wavelength of EUV lithography is 13.5nm. In order to support the technology after 12 ~ 10 nm, various super-resolution technologies (RET) are necessary. However, if RET is introduced, the problem of rising etching cost will appear in EUV lithography again this time. Etching technicians pointed out that "EUV lithography is in danger of missing the opportunity of mass production introduction", and this view is more and more likely to appear.
Intel introduced three-dimensional transistors in the 22nm process, and other companies began to import them in the 15mm process.
In 2011, the biggest topic related to semiconductor technology is the practicality of three-dimensional transistors. In May 2011, Intel Corporation announced that it would adopt three-dimensional transistors. The structure of the company's three-dimensional transistor "Tri-Gate" is similar to that of Fin FET, and gate electrodes are arranged on both sides of the channel and in the upper three directions. It will be used in the 22nm microprocessor which will be mass-produced at the end of 2011.
Many companies in the industry, such as TSMC and GLOBALFOUNDRIES, have indicated that they will introduce three-dimensional transistors from the 15nm process that began mass production around 2014. Regarding this difference, TSMC said, "According to our research results, the plane structure can give full play to its performance before 20nm". In addition, TSMC also admits that if three-dimensional transistors are introduced, there will be a huge burden in design support. The 22/20nm process can achieve the required performance by using both planar structure and three-dimensional structure. Because Intel Corporation is a chip manufactured from its own company, the design support load is light, while TSMC and GLOBALFOUNDRIES are contracted to manufacture chips from other companies, so the design support is more important. It is very likely that this difference in business forms makes the lead-in time of three-dimensional transistors inconsistent.
In addition, not only the transistor structure, but also its composition will change greatly in the future. In order to improve the performance of transistors, we are considering replacing silicon (Si) which has been used for a long time with germanium (Ge) and III-IV materials. By advancing this improvement, transistor technology is expected to be miniaturized to 8nm.
